This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-095899, filed Mar. 29, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, particularly, to a gate electrode structure of a damascene gate transistor prepared by forming a gate electrode groove in an insulating film, followed by burying a gate electrode in the groove and a method for manufacturing the particular gate electrode structure.
2. Description of the Related Art
A transistor using a metallic material for forming the gate electrode is considered hopeful as a next-generation transistor because this type of transistor is free from deteriorations caused by, for example, a voltage drop derived from the depletion of the gate or the gate resistance, like a transistor using polycrystalline silicon (polysilicon) for forming the gate electrode. However, a metallic material such as W, Al or Cu is incapable of withstanding a high temperature heat treatment. Therefore, the activation temperature for forming the source-drain regions after the processing of the gate electrode should not affect the gate electrode, although the gate electrode is affected by the activation temperature noted above in usual transistor forming processes. As a means for preventing the gate electrode from being affected by the activation temperature in question, a damascene metal gate or replacement gate transistor has attracted attention as described in, for example, xe2x80x9cInternational Electron Devices Meeting Technical Digest, 1998, pp. 777-780, pp. 785-788xe2x80x9d. The damascene gate or replacement gate transistor is prepared as follows. In the first step, a dummy gate is formed, followed by implanting impurity ions with the dummy gate used as a mask. Then, the implanted impurity is activated so as to form source-drain regions. Further, after removal of the dummy gate, ion implantation is performed for forming a channel region, followed by forming again a gate insulating film and subsequently burying a metal electrode.
However, in the case of using a metallic material for forming a gate electrode, it is difficult to adjust the work function by ion implantation, although ion implantation is employed for adjusting the work function in the case of using polysilicon for forming the gate electrode. Therefore, it is unavoidable to select a material having a work function positioned in the central region of the band gap of silicon, such as TiN, for forming the gate electrode for a CMOS transistor, with the result that it is difficult to realize a low voltage/low threshold value required for a next-generation transistor of reduced the power consumption.
Under the circumstances, in order to lower the threshold value, it is necessary to employ a buried channel structure in which an impurity having a conductivity type opposite that of the semiconductor substrate is implanted in the channel surface.
However, an impurity having a conductivity type opposite that of the impurity used for the adjustment of the threshold value of a surface channel type transistor is implanted in the buried channel type transistor, with the result that a punch-through tends to take place between the source and drain regions, which deteriorates the short channel characteristics.
On the other hand, proposed is a so-called xe2x80x9cpocketxe2x80x9d or xe2x80x9chaloxe2x80x9d structure in which an impurity for the punch-through stopper is obliquely introduced by ion implantation after formation of the dummy gate, as shown in FIG. 19A, for improving the short channel characteristics, as described in, for example, xe2x80x9cInternational Electron Devices Meeting Technical Digest, 1998, pp. 789-792xe2x80x9d.
In the case of using this type of transistor, the impurity concentration is rendered high in the channel portion if the channel is long, compared with a short channel, as shown in FIGS. 19B and 19C, so as to make it possible to sufficiently suppress the punch-through between the source and drain regions.
In this particular structure, however, a junction is formed between the source-drain regions having a high impurity concentration and the region of a high impurity concentration in the halo structure, giving rise to the problems that the junction capacitance between the source-drain regions and the semiconductor substrate, and that the junction leak current is increased. Also, as described previously, a transistor which with a metal gate is considered hopeful as a next generation transistor. However, the activation temperature for forming the source-drain regions after the processing of the gate electrode should not affect the gate electrode, although the gate electrode is affected by the activation temperature noted above in the ordinary process for forming a transistor. As a means for preventing the gate electrode from being affected by the activation temperature in question, a damascene metal gate in which the metal noted above is buried attracts attention. However, since the work function of the metal electrode is positioned in the vicinity of the mid gap of silicon, it is unavoidable to that the buried channel structure has poor short channel characteristics.
It should also be noted that, since a gate insulating film is formed again after removal of the dummy gate once formed and the oxide film positioned below the dummy gate for burying an electrode material in the gate insulating film formed again, it is highly possible for a problem to be generated in terms of the reliability of the gate edge.
According to a first aspect of the present invention, there is provided a semiconductor device, comprising a semiconductor substrate; a pair of first diffusion layers formed within the semiconductor substrate; a gate insulating film formed on that portion of the semiconductor substrate which is positioned between the paired diffusion layers; a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gate portion, a first width in a channel direction of the first gate portion being substantially equal to a width in the channel direction of the gate insulating film, and a second width in the channel direction of the second gate portion being larger than the first width; a gate side wall insulating film including a first side wall portion formed on a side surface of the first gate portion and on a side surface of the gate insulating film and a second side wall portion formed on a side surface of the second gate portion; and a second diffusion layer formed apart from the first diffusion layers within that portion of the semiconductor substrate which is positioned below the gate insulating film.
According to a second aspect of the present invention, there is provided a semiconductor device, comprising a semiconductor substrate; a pair of first diffusion layers formed within the semiconductor substrate; a gate insulating film including a first insulating film portion formed on that portion of the semiconductor substrate which is positioned between the first diffusion layers and a second insulating film portion positioned on both edges of the first insulating film portion, a thickness of the second insulating film portion being larger than a thickness of the first insulating film portion; a gate electrode formed on the gate insulating film; a gate side wall insulating film formed on a side surface of the gate electrode and on a side surface of the second insulating film portion; and a second diffusion layer formed apart from the first diffusion layers within that portion of the semiconductor substrate which is positioned below the first insulating film portion.
According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising forming a first material layer on a semiconductor substrate; forming a second material layer comprising a first width on the first material layer; partly removing the first material layer to leave the first material layer comprising a second width smaller than the first width below the second material layer; introducing an impurity into the semiconductor substrate with the second material layer used as a mask to form an extension region; forming a gate side wall insulating film on a side surfaces of the first and second material layers, the gate side wall insulating film including a first side wall portion formed on the side surface of the first material layer and a second side wall portion formed on the side wall of the second material layer; introducing an impurity into the semiconductor substrate with the gate side wall insulating film and the second material layer used as a mask to form source and drain regions; forming an interlayer insulating film on the semiconductor substrate, on the second material layer and on the gate side wall insulating film, followed by removing the interlayer insulating film until the second material layer is exposed; removing the first and second material layers to form a groove; introducing an impurity through the groove into the semiconductor substrate to form a second diffusion layer apart from the extension region within that portion of the semiconductor substrate which is positioned below the groove; forming a gate insulating film on that portion of the semiconductor substrate which is positioned within the groove; and forming a gate electrode on the gate insulating film positioned within the groove.
According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising forming a gate insulating film on a semiconductor substrate; forming a second material layer comprising a predetermined shape on the gate insulating film; thermally oxidizing the second material layer and the semiconductor substrate to form a first insulating film on an upper surface and a side surface of the second material layer and to increase a thickness in a portion of the gate insulating film; partly removing the first insulating film and the gate insulating film to form a first gate side wall insulating film on the side surface of the second material layer and to form a second insulating film portion of the gate insulating film positioned below both edges of the second material layer comprising a thickness larger than a thickness of the first insulating film portion of the gate insulating film below a central portion of the second material layer; introducing an impurity into the semiconductor substrate with the second material layer and the first gate side wall insulating film used as a mask to form an extension region; forming a second gate side wall insulating film on a side surface of the first gate side wall insulating film; introducing an impurity into the semiconductor substrate with the second material layer and the first and second gate side wall insulating films used as a mask to form source-drain regions; forming an interlayer insulating film on the semiconductor substrate, the second material layer and the first and second gate side wall insulating films, followed by removing the interlayer insulating film until the second material layer is exposed; removing the second material layer to form a groove; introducing an impurity through the groove into the semiconductor substrate to form a second diffusion layer apart from the extension region within that portion of the semiconductor substrate which is positioned below the first insulating film portion; and forming a gate electrode on the gate insulating film positioned within the groove.